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| HT46R232/HT46C232 A/D Type 8-Bit MCU Technical Document * Tools Information * FAQs * Application Note - HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series - HA0013E HT48 & HT46 LCM Interface Design - HA0017E Controlling the Read/Write Function of the HT24 Series EEPROM Using the HT49 Series MCUs Features * Operating voltage: * Up to 0.5ms instruction cycle with 8MHz system clock fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V * 40 bidirectional I/O lines (max.) * 1 interrupt input shared with an I/O line * Two 16-bit programmable timer/event counter with at VDD=5V * 8-level subroutine nesting * 8 channels 10-bit resolution A/D converter * 4-channel 8-bit PWM output shared with four I/O lines * Bit manipulation instruction * 16-bit table read instruction * 63 powerful instructions * All instructions in one or two machine cycles * Low voltage reset function * I2C Bus (slave mode) * 28-pin SKDIP/SOP, 48-pin SSOP packages overflow interrupt * On-chip crystal and RC oscillator * Watchdog Timer * 409616 program memory * 1928 data memory RAM * Supports PFD for sound generation * HALT function and wake-up feature reduce power consumption General Description The HT46R232/HT46C232 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The mask version HT46C232 is fully pin and functionally compatible with the OTP version HT46R232 device. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter, Pulse Width Modulation function, I2C interface, HALT and wake-up functions, enhance the versatility of these devices to suit a wide range of A/D application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. I C is a trademark of Philips Semiconductors. 2 Rev. 1.40 1 November 23, 2005 HT46R232/HT46C232 Block Diagram In te rru p t C ir c u it STACK P ro g ra m EPROM P ro g ra m C o u n te r IN T C TM R0C TM R0 PFD0 TM R1C TM R1 PFD1 M U X M U X P r e s c a le r TM R0 TM R1 fS YS fS YS /4 BP In s tr u c tio n R e g is te r MP M U X WDT DATA M e m o ry M U fS X YS /4 W DT OSC PF0~PF7 PFC PF P o rt F In s tr u c tio n D ecoder ALU T im in g G e n e ra to r MUX PA5 PW PDC M P o rt D STATUS PD P D 0 /P W M 0 ~ P D 3 /P W PD 4~PD 7 M3 S h ifte r PCC PC P o rt C PC 0~PC7 8 -C h a n n e l A /D C o n v e rte r OSC2 OS RE VD VS S S D C1 ACC H ALT LVR E N /D IS PBC PB PAC PA IC Bus S la v e M o d e 2 P o rt B P B 0 /A N 0 ~ P B 7 /A N 7 PA PA PA PA PA PA 0~ 3/ 4 5/ 6/ 7/ PA2 PFD IN T SDA SCL P o rt A Pin Assignment P B 5 /A N 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P B 4 /A N 4 P A 3 /P F D PA2 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 P B 5 /A N 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P B 4 /A N 4 P A 3 /P F D PA2 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 VSS PC0 PC1 PC2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P B 6 /A N 6 P B 7 /A N 7 PA4 P A 5 /IN T P A 6 /S D A P A 7 /S C L OSC2 OSC1 VDD RES P D 1 /P W M 1 /T M R 1 P D 0 /P W M 0 PC4 PC3 NC PF3 PF2 PF1 PD7 PD6 PD5 PD4 VSS PF0 TM R0 PC0 PC1 PC2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P B 6 /A N 6 P B 7 /A N 7 PA4 P A 5 /IN T P A 6 /S D A P A 7 /S C L PF4 PF5 PF6 PF7 OSC2 OSC1 VDD RES TM R1 P D 3 /P W M 3 P D 2 /P W M 2 P D 1 /P W M 1 P D 0 /P W M 0 PC7 PC6 PC5 PC4 PC3 H T 4 6 R 2 3 2 /H T 4 6 C 2 3 2 2 8 S K D IP -A /S O P -A H T 4 6 R 2 3 2 /H T 4 6 C 2 3 2 4 8 S S O P -A Rev. 1.40 2 November 23, 2005 HT46R232/HT46C232 Pin Description Pin Name PA0~PA2 PA3/PFD PA4 PA5/INT PA6/SDA PA7/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 PC0~PC7 PD0/PWM0 PD1/PWM1 PD2/PWM2 PD3/PWM3 PD4~PD7 PF0~PF7 TMR0 TMR1 RES VSS VDD OSC1 OSC2 I/O Options Pull-high Wake-up PA3 or PFD I/O or Serial Bus Description Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by option (bit option). Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). The PFD and INT are pin-shared with PA3 and PA5, respectively. Once the I2C Bus function is used, the internal registers related to PA6 and PA7 cannot be used. I/O I/O Pull-high Bidirectional 8-bits input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are automatically disabled. I/O Pull-high Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: byte option). Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: byte option). The PWM0/PWM1/PWM2/ PWM3 output function are pin-shared with PD0/PD1/PD2/PD3 (depending on the PWM options). Bidirectional 8-bit input/output port. Software instructions determine the CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: byte option). Timer/Event Counter 0 Schmitt trigger input (without pull-high resistor) Timer/Event Counter 1 Schmitt trigger input (without pull-high resistor). Schmitt trigger reset input, active low Negative power supply, ground Positive power supply OSC1 and OSC2 are connected to an RC network or a crystal (by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. I/O Pull-high PWM I/O I I I 3/4 3/4 I O Pull-high 3/4 3/4 3/4 3/4 3/4 Crystal or RC Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.40 3 November 23, 2005 HT46R232/HT46C232 D.C. Characteristics Test Conditions Symbol Parameter VDD VDD Operating Voltage 3/4 3V Operating Current (Crystal OSC) 5V IDD2 3V Operating Current (RC OSC) 5V IDD3 Operating Current (Crystal OSC, RC OSC) Standby Current (WDT Enabled) 5V ISTB2 3V Standby Current (WDT Disabled) 5V VIL1 VIH1 VIL2 VIH2 VLVR IOL Input Low Voltage for I/O Ports, TMR0, TMR1 and INT Input High Voltage for I/O Ports, TMR0, TMR1 and INT Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset Voltage I/O Port Sink Current 5V IOH 3V I/O Port Source Current 5V RPH VAD EAD IADC 3V Pull-high Resistance 5V A/D Input Voltage A/D Conversion Error Additional Power Consumption if A/D Converter is Used 3/4 3/4 3V 5V 3/4 3/4 3/4 3/4 VOH=0.9VDD 3/4 3/4 3/4 3/4 3/4 3V 3/4 3/4 3/4 3/4 3/4 VOL=0.1VDD No load, system HALT 5V 3V No load, system HALT Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz ADC disable No load, fSYS=4MHz ADC disable No load, fSYS=8MHz ADC disable 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 2.7 4 10 -2 -5 20 10 0 3/4 3/4 3/4 3/4 3/4 0.6 2 0.8 2.5 4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3 8 20 -4 -10 60 30 3/4 0.5 0.5 1.5 5.5 5.5 1.5 4 1.5 4 8 5 10 1 2 0.3VDD VDD 0.4VDD VDD 3.3 3/4 3/4 3/4 3/4 100 50 VDD 1 1 3 V V mA mA mA mA mA mA mA mA mA V V V V V mA mA mA mA kW kW V LSB mA mA Min. Typ. Max. Unit Ta=25C IDD1 ISTB1 Rev. 1.40 4 November 23, 2005 HT46R232/HT46C232 A.C. Characteristics Test Conditions Symbol Parameter VDD fSYS System Clock Timer I/P Frequency (TMR0/TMR1) Watchdog Oscillator Period 5V tRES tSST tINT tAD tADC tADCS tIIC External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time I2C Bus Clock Period 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4 Connect to external pull-high resistor 2kW 400 400 0 0 45 32 1 3/4 1 1 3/4 3/4 64 3/4 3/4 3/4 3/4 90 65 3/4 1024 3/4 3/4 76 32 3/4 4000 8000 4000 8000 180 130 3/4 3/4 3/4 3/4 3/4 3/4 3/4 kHz kHz kHz kHz ms ms ms *tSYS ms ms tAD tAD *tSYS Min. Typ. Max. Unit Ta=25C fTIMER tWDTOSC Note: *tSYS=1/fSYS Rev. 1.40 5 November 23, 2005 HT46R232/HT46C232 Functional Description Execution Flow The system clock is derived from either a crystal or an RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) is 12 bits wide and it controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 4096 addresses. After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction. The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. When a control transfer takes place, an additional dummy cycle is required. T2 T3 T4 T1 T2 T3 T4 S y s te m C lo c k T1 T2 T3 T4 T1 O S C 2 ( R C o n ly ) PC PC PC+1 PC+2 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Mode Initial Reset External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow A/D Converter Interrupt I2C Bus Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine Program Counter *11 0 0 0 0 0 0 *11 #11 S11 *10 0 0 0 0 0 0 *10 #10 S10 *9 0 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 1 @4 #4 S4 *3 0 0 1 1 0 0 @3 #3 S3 *2 0 1 0 1 0 1 @2 #2 S2 *1 0 0 0 0 0 0 @1 #1 S1 *0 0 0 0 0 0 0 @0 #0 S0 Program Counter + 2 Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits Rev. 1.40 6 November 23, 2005 HT46R232/HT46C232 Program Memory - EPROM The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 409616 bits which are addressed by the program counter and table pointer. Certain locations in the ROM are reserved for special usage: * Location 000H * Location 00CH Location 00CH is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. * Location 010H Location 000H is reserved for program initialization. After chip reset, the program always begins execution at this location. * Location 004H Location 010H is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H. * Location 014H Location 004H is reserved for the external interrupt service program. If the INT input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004H. * Location 008H This area is reserved for the I2C Bus interrupt service program. If the I2C Bus interrupt resulting from a slave address is match or completed one byte of data transfer, and if the interrupt is enable and the stack is not full, the program begins execution at location 014H. * Table location Location 008H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H. 000H 004H 008H 00CH 010H 014H D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e A /D C o n v e rte r In te rru p t I2C B u s In te rru p t P ro g ra m M e m o ry Any location in the ROM can be used as a look-up table. The instructions TABRDC [m] (the current page, page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (Table Higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH. The TBLH is read only, and the table pointer (TBLP) is a read/write register (07H), indicating the table location. Before accessing the table, the location should be placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas may function as a normal ROM depending upon the users requirements Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At the state of a subroutine call or an interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of the subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous Table Location n00H nFFH F00H FFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 6 b its N o te : n ra n g e s fro m 0 to F Program Memory Instruction TABRDC [m] TABRDL [m] *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0 Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program counter bits Rev. 1.40 7 November 23, 2005 HT46R232/HT46C232 value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure more easily. If the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return addresses are stored). Data Memory - RAM The data memory (RAM) is designed with 2318 bits, and is divided into two functional groups, namely; special function registers (398 bits) and general purpose data memory (1928 bits) most of which are readable/writeable, although some are read only. The special function registers are overlapped in any banks. Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), a Timer/Event Counter 0 (TMR0H:0CH; TMR0L:0DH), a Timer/Event Counter 0 control register (TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH; TMR1L:10H), a Timer/Event Counter 1 control register (TMR1C; 11H), Interrupt control register 1 (INTC1;1EH), PWM data register (PWM0;1AH, PWM1;1BH, PWM2;1CH, PWM3;1DH), the I2C Bus slave address register (HADR;20H), the I2C Bus control register (HCR;21H), the I2C Bus status register (HSR;22H), the I 2 C Bus data register (HDR;23H),the A/D result lower-order byte register (ADRL;24H), the A/D result higher-order byte register (ADRH;25H), the A/D control register (ADCR;26H), the A/D clock setting register (ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H, PF; 28H) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H, PFC;29H). The remaining space before the 40H is reserved for future expanded usage and reading these locations will get 00H. The space before 40H is overlapping in each bank. The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). The space before 40H is overlapping in each bank. 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 30H 3FH 40H HADR HCR HSR HDR ADRL ADRH ADCR ACSR PF PFC STATUS IN T C 0 TM R0H TM R0L TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC PW M0 PW M1 PW M2 PW M3 IN T C 1 S p e c ia l P u r p o s e D a ta M e m o ry ACC PCL TBLP TBLH In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 FFH G e n e ra l P u rp o s e D a ta M e m o ry (1 9 2 B y te s ) :U nused R e a d a s "0 0 " RAM Mapping Rev. 1.40 8 November 23, 2005 HT46R232/HT46C232 Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H. While, writing it indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers used to access the RAM by combining corresponding indirect addressing registers. Accumulator - ACC The accumulator is closely related to ALU operations. It is also mapped to location 05H of the RAM and capable of operating with immediate data. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: * Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....) information and controls the operation sequence. Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those intended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Interrupts The device provides an external interrupt, two internal timer/event counter interrupt, the A/D converter interrupt and the I2C Bus interrupts. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of INTC0 and INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. Function The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS The status register (0AH) is 8 bits wide and contains, a carry flag (C), an auxiliary carry flag (AC), a zero flag (Z), an overflow flag (OV), a power down flag (PDF), and a Watchdog time-out flag (TO). It also records the status Bit No. 0 Label C C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register 1 2 3 4 5 6, 7 AC Z OV PDF TO 3/4 Rev. 1.40 9 November 23, 2005 HT46R232/HT46C232 All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit 4 of INTC0) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of INTC0), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the T0F bit is set, a subroutine call to location 08H occurs. The related interrupt request flag (T0F) is reset, and the EMI bit is cleared to disable further maskable interrupts. The Timer/Event Counter 1 is operated in the same manner but its related interrupt request flag is T1F (bit 6 of INTC0) and its subroutine call location is 0CH. The A/D converter interrupt is initialized by setting the A/D converter request flag (ADF; bit 4 of INTC1), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a subroutine call to location 10H will occur. The related interrupt request flag (ADF) will be reset and the EMI bit cleared to disable further interrupts. The I2C Bus interrupt is initialized by setting the I2C Bus interrupt request flag (HIF; bit 5 of INTC1), caused by a slave address match (HAAS=1) or one byte of data transfer is completed. When the interrupt is enabled, the stack is not full and the HIF bit is set, a subroutine call to location 14H will occur. The related interrupt request flag (HIF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Function Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the external interrupt (1= enabled; 0= disabled) Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled) Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled) External interrupt request flag (1= active; 0= inactive) Internal Timer/Event Counter 0 request flag (1= active; 0= inactive) Internal Timer/Event Counter 1 request flag (1= active; 0= inactive) For test mode used only. Must be written as 0; otherwise may result in unpredictable operation. INTC0 (0BH) Register Bit No. 0 1 2, 3 4 5 6, 7 Label EADI EHI 3/4 ADF HIF 3/4 Function Control the A/D converter interrupt (1= enabled; 0=disabled) Control the I2C Bus interrupt (1= enabled; 0= disabled) Unused bit, read as 0 A/D converter request flag (1= active; 0= inactive) I2C Bus interrupt request flag (1= active; 0= inactive) Unused bit, read as 0 INTC1 (1EH) Register Rev. 1.40 10 November 23, 2005 Bit No. 0 1 2 3 4 5 6 7 Label EMI EEI ET0I ET1I EIF T0F T1F 3/4 HT46R232/HT46C232 Interrupt Source External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow A/D Converter Interrupt I2C Bus Interrupt Priority 1 2 3 4 5 Vector 04H 08H 0CH 10H 14H tions. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz). The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) decided by options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by a option. If the watchdog timer is disabled, all the executions related to the WDT result in no operation. Once an internal WDT oscillator (RC oscillator with period 65ms at 5V normally) is selected, it is divided by 212~215 (by option to get the WDT time-out period). The WDT time-out minimum period is 300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection from the WDT option, longer time-out periods can be realized. If the WDT time-out is selected 215, the maximum time-out period is divided by 215~216about 2.1s~4.3s. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm reset only the program counter and stack pointer are reset to zero. To clear the contents of WDT, three methods are adopted; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions include CLR WDT and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the option - CLR WDT times selection option. If the CLR WDT is selected (i.e. 11 November 23, 2005 The Timer/Event Counter 0/1 interrupt request flag (T0F, T1F), external interrupt request flag (EIF), A/D converter request flag (ADF), the I2C Bus interrupt request flag (HIF), enable timer/event counter bit (ET0I, ET1I), enable external interrupt bit (EEI), enable A/D converter interrupt bit (EADI), enable I2C Bus interrupt bit (EHI) and enable master interrupt bit (EMI) constitute an interrupt control register 0 (INTC0) and an interrupt control register 1 (INTC1) which are located at 0BH and 1EH in the data memory. EMI, EEI, ET0I, ET1I, EADI, EHI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F, T1F, EIF, ADF, HIF) are set, they will remain in the INTC0 and INTC1 register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There are two oscillator circuits in the microcontroller. V OSC1 DD 470pF OSC1 OSC2 C r y s ta l O s c illa to r fS YS /4 RC OSC2 O s c illa to r System Oscillator Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined by the option. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. If an RC oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 30kW to 750kW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process varia- Rev. 1.40 HT46R232/HT46C232 S y s te m C lo c k /4 M ask o p tio n s e le c t W DT OSC fs D iv id e r fs/2 8 W D T P r e s c a le r M a s k O p tio n W D T C le a r CK R T CK R T T im e 2 1 5/fS 2 1 4/fS 2 1 3/fS 2 1 2/fS -o ~ ~ ~ ~ ut 21 21 21 21 6 5 R eset /fS /fS 4 /fS 3 /fS Watchdog Timer CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out. If the WDT time-out period is selected fs/212 (option), the WDT time-out period ranges from fs/212~fs/213, since the CLR WDT or CLR WDT1 and CLR WDT2 instructions only clear the last two stages of the WDT. Power Down Operation - HALT The HALT mode is initialized by the HALT instruction and results in the following... * The system oscillator turned off but the WDT oscillator the interrupt is enabled and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. If wake-up event occurs, it takes 1024 fSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the wake-up results in the next instruction execution, this will be executed performed immediately after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset may occur: * RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation * * * * keeps running (if the WDT oscillator or the real time clock is selected). The contents of the on-chip RAM and registers remain unchanged The WDT will be cleared and start recounting (if the WDT clock source is from the WDT oscillator or the real time clock) All of the I/O ports maintain their original status The PDF flag is set and the TO flag is cleared The system quits the HALT mode by an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. After examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or by executing the CLR WDT instruction and is set when executing the HALT instruction. On the other hand, the TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP; and leaves the others in their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by the option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. But if The WDT time-out during HALT differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and SP, leaves the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. Examining the PDF and TO flags, the program can distinguish between different chip resets. V DD 0 .0 1 m F * 100kW RES 10kW 0 .1 m F * Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.40 12 November 23, 2005 HT46R232/HT46C232 VDD RES S S T T im e - o u t C h ip R eset tS ST + tO PD from an external source or an internal clock source. An internal clock source comes from fSYS/4. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. There are six registers related to the Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) and the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing TMR0L (TMR1L) will only put the written data to an internal lower-order byte buffer (8-bit) and writing TMR0H (TMR1H) will transfer the specified data and the contents of the lower-order byte buffer to TMR0H (TMR1H) and TMR0L (TMR1L) registers, respectively. The Timer/Event Counter 1/0 preload register is changed by each writing TMR0H (TMR1H) operations. Reading TMR0H (TMR1H) will latch the contents of TMR0H (TMR1H) and TMR0L (TMR1L) counters to the destination and the lower-order byte buffer, respectively. Reading the TMR0L (TMR1L) will read the contents of the lower-order byte buffer. The TMR0C (TMR1C) is the Timer/Event Counter 0 (1) control register, which defines the operating mode, counting enable or disable and an active edge. The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C) bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR0, TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR0, TMR1), and the counting is based on the internal selected clock source. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFFFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (T0F; bit 5 of INTC0, T1F; bit 6 of INTC0). In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to 1, after the TMR0 (TMR1) has received a transient from low to high (or high to low if the T0E/T1E bit is 0), it will start counting until the TMR0 (TMR1) returns to the original level and resets the T0ON/T1ON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the T0ON/T1ON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. 13 November 23, 2005 Reset Timing Chart HALT W DT RES W a rm R eset W DT T im e - o u t R eset E x te rn a l C o ld R eset OSC1 SST 1 0 - b it R ip p le C o u n te r P o w e r - o n D e te c tio n Reset Configuration TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT Note: u stands for unchanged To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system awakes from the HALT state or during power up. Awaking from the HALT state or system power up an SST delay is added. An extra SST delay is added during power up period, and any wake-up from HALT may enable only the SST delay. The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler, Divider WDT Timer/event Counter Input/output Ports Stack Pointer Timer/Event Counter Two Timer/Event Counters (TMR0,TMR1) are implemented in the microcontroller. The timer/event counter 0 contains an 16-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS. The timer/event counter 1 contains an 16-bit programmable count-up counter and the clock may come Rev. 1.40 000H Disable Cleared Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack HT46R232/HT46C232 The registers states are summarized in the following table. Register MP0 MP1 ACC Program Counter TBLP TBLH STATUS INTC0 TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C PA PAC PB PBC PC PCC PD PDC PWM0 PWM1 PWM2 PWM3 INTC1 HADR HCR HSR HDR ADRL ADRH ADCR ACSR PF PFC Note: Reset (Power On) xxxx xxxx xxxx xxxx xxxx xxxx 000H xxxx xxxx xxxx xxxx --00 xxxx -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 --00 xxxx xxx0--0 0--100- -0-1 xxxx xxxx xx-- ---xxxx xxxx 0100 0000 1--- --00 1111 1111 1111 1111 * stands for warm reset u stands for unchanged x stands for unknown 14 November 23, 2005 WDT Time-out RES Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu uuuu uuuu --1u uuuu -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 --00 xxxx xxx0--0 0--100- -0-1 xxxx xxxx xx-- ---xxxx xxxx 0100 0000 1--- --00 1111 1111 1111 1111 uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu uuuu uuuu --uu uuuu -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 --00 xxxx xxx0--0 0--100- -0-1 xxxx xxxx xx-- ---xxxx xxxx 0100 0000 1--- --00 1111 1111 1111 1111 RES Reset (HALT) uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu uuuu uuuu --01 uuuu -000 0000 xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1--1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 --00 xxxx xxx0--0 0--100- -0-1 xxxx xxxx xx-- ---uuuu uuuu 0100 0000 1--- --00 1111 1111 1111 1111 WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu 000H uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu --uu uuuu uuuu--u u--uuuu uuuu uuuu uuuu uu-- ---uuuu uuuu uuuu uuuu u--- --uu uuuu uuuu uuuu uuuu Rev. 1.40 HT46R232/HT46C232 PW M (6 + 2 ) o r (7 + 1 ) C o m p a re fS YS T o P D 0 /P D 1 /P D 2 /P D 3 C ir c u it D a ta B u s L o w B y te B u ffe r 8 - s ta g e P r e s c a le r 8 -1 M U X T0PSC 2~T0PSC 0 TM R0 T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l f IN T T0M 1 T0M 0 1 6 - B it P r e lo a d R e g is te r R e lo a d H ig h B y te L o w B y te O v e r flo w to In te rru p t 1 6 - B it T im e r /E v e n t C o u n te r PFD0 Timer/Event Counter 0 D a ta B u s L o w B y te B u ffe r T fS YS /4 f IN TM R1 T1E T1M 1 T1M 0 T1O N T1M 1 T1M 0 1 6 - B it P r e lo a d R e g is te r P u ls e W id th M e a s u re m e n t M o d e C o n tro l R e lo a d H ig h B y te Low B y te O v e r flo w to In te r r u p t 1 6 - B it T im e r /E v e n t C o u n te r PFD1 Timer/Event Counter 1 PFD0 M PFD1 U X 1 /2 PFD P A 3 D a ta C T R L PFD S o u r c e O p tio n PFD Source Option To enable the counting operation, the Timer ON bit (T0ON: bit 4 of TMR0C; T10N: bit 4 of TMR1C) should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by options. Only one PFD (PFD0 or PFD1) can be applied to PA3 by options. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing SET [PA].3 instruction to enable PFD output and executing CLR [PA].3 instruction to disable PFD output. Rev. 1.40 15 In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. When the timer/event counter (reading TMR0/TMR1) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR0/TMR1 is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. November 23, 2005 HT46R232/HT46C232 The bit0~bit2 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal. The timer prescaler is also used as the PWM counter. Bit No. Label Function Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 Defines the operating mode, T0M1, T0M0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register Bit No. 0~2 Label 3/4 Unused bit, read as 0 Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 Defines the operating mode, T1M1, T1M0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register Function 0 1 2 T0PSC0 T0PSC1 T0PSC2 3 T0E 4 5 T0ON 3/4 6 7 T0M0 T0M1 3 T1E 4 5 T1ON 3/4 6 7 T1M0 T1M1 Rev. 1.40 16 November 23, 2005 HT46R232/HT46C232 Input/Output Ports There are 40 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC, PD and PF, which are mapped to the data memory of [12H], [14H], [16H], [18H] and [28H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, [18H] or 28H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC, PDC, PFC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modifywrite instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H, 19H and 29H. After a chip reset, these input/output lines remain at high levels or floating state (depends on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H, 16H 18H or 28H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, theres none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. The PA3 and PA5 are pin-shared with the PFD and INT pins respectively. If the PFD option is selected, the output signal in output mode of PA3 will be the PFD signal generated by timer/event counter overflow signal. The input mode always remain in its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data register only. Writing 1 to PA3 data register will enable the PFD output function and writing 0 will force the PA3 to remain at 0. The I/O functions of PA3 are shown below. I/O I/P Mode (Normal) PA3 Note: Logical Input O/P (Normal) Logical Output I/P (PFD) Logical Input O/P (PFD) PFD (Timer on) The PFD frequency is the timer/event counter overflow frequency divided by 2. The PB can also be used as A/D converter inputs. The A/D function will be described later. There is a PWM function shared with PD0/PD1/PD2/PD3. If the PWM function is enabled, the PWM0/PWM1/PWM2/PWM3 signal will appear on PD0/PD1/PD2/PD3 (if PD0/PD1/ PD2/PD3 is operating in output mode). The I/O functions of PD0/PD1/PD2/PD3 are as shown. V DD C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D CK Q S Q PU D a ta B it Q D CK S M U X Q W r ite D a ta R e g is te r PA PA PA PA PA PA PB PC PD PD PD PD PD PF 4 5 /IN 6 /S 7 /S 0 /A 0~P 0 /P 1 /P 2 /P 3 /P 4~P 0~P 0~PA2 3 /P F D T DA CL N0~ C7 WM WM WM WM D7 F7 0 1 2 3 P B 7 /A N 7 [P A 3 , P F D ] o r [P D 0 ,P W M 0 ] o r [P D 1 ,P W M 1 ] o r [P D 2 ,P W M 2 ] o r [P D 3 ,P W M 3 ] R e a d D a ta R e g is te r S y s te m W a k e -u p ( P A o n ly ) IN T fo r P A 5 O n ly M U X E N (P F D o r PW M 0~PW M 3) O P0~O P7 Input/Output Ports Rev. 1.40 17 November 23, 2005 HT46R232/HT46C232 I/O Mode PD0~ PD3 I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PWM) Logical Input O/P (PWM) PWM0~ PWM3 PDC.2/PDC.3 =0), writing 1 to PD0/PD1/PD2/PD3 data register will enable the PWM output function and writing 0 will force the PD0/PD1/PD2/PD3 to stay at 0. A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). Each modulation cycle has 64 PWM input clock period. In a (6+2) bit PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. The group 2 is denoted by AC which is the value of PWM.1~PWM.0. In a (6+2) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter Modulation cycle i (i=0~3) AC (0~3) i fS YS /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M PW M 2 6 /6 4 m o d u la tio n p e r io d : 6 4 /fS M o d u la tio n c y c le 0 YS 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4 2 6 /6 4 M o d u la tio n c y c le 1 PW M 2 6 /6 4 M o d u la tio n c y c le 2 c y c le : 2 5 6 /fS YS 2 5 /6 4 M o d u la tio n c y c le 3 2 6 /6 4 M o d u la tio n c y c le 0 (6+2) PWM Mode fS YS /2 [P W M ] = 1 0 0 PW M [P W M ] = 1 0 1 PW M [P W M ] = 1 0 2 PW M [P W M ] = 1 0 3 PW M 5 2 /1 2 8 PW M m o d u la tio n p e r io d : 1 2 8 /fS M o d u la tio n c y c le 0 PW M c y c le : 2 5 6 /fS YS YS 5 0 /1 2 8 5 0 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 0 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8 5 2 /1 2 8 M o d u la tio n c y c le 1 M o d u la tio n c y c le 0 (7+1) PWM Mode Rev. 1.40 18 November 23, 2005 HT46R232/HT46C232 A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle0~modulation cycle 1). Each modulation cycle has 128 PWM input clock period. In a (7+1) bits PWM function, the contents of the PWM register is divided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.1. The group 2 is denoted by AC which is the value of PWM.0. In a (7+1) bits mode PWM cycle, the duty cycle of each modulation cycle is shown in the table. Parameter AC (0~1) i Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is power off to reduce power consumption Indicates end of A/D conversion. (0 = end of A/D conversion) Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialization. START Starts the A/D conversion. (0(R)1(R)0= start; 0(R)1= Reset A/D converter and set EOCB to 1) ADCR (26H) Register Rev. 1.40 19 November 23, 2005 HT46R232/HT46C232 PCR2 0 0 0 0 1 1 1 1 PCR1 0 0 1 1 0 0 1 1 PCR0 0 1 0 1 0 1 0 1 7 PB7 PB7 PB7 PB7 PB7 PB7 PB7 AN7 6 PB6 PB6 PB6 PB6 PB6 PB6 PB6 AN6 5 PB5 PB5 PB5 PB5 PB5 PB5 AN5 AN5 4 PB4 PB4 PB4 PB4 PB4 AN4 AN4 AN4 3 PB3 PB3 PB3 PB3 AN3 AN3 AN3 AN3 2 PB2 PB2 PB2 AN2 AN2 AN2 AN2 AN2 1 PB1 PB1 AN1 AN1 AN1 AN1 AN1 AN1 0 PB0 AN0 AN0 AN0 AN0 AN0 AN0 AN0 Port B Configuration Bit No. Label Function Selects the A/D converter clock source 00= system clock/2 01= system clock/8 10= system clock/32 11= undefined Unused bit, read as 0 For test mode used only ACSR (27H) Register ACS2 0 0 0 0 1 1 1 1 ACS1 0 0 1 1 0 0 1 1 ACS0 0 1 0 1 0 1 0 1 Analog Input Channel Selection Register ADRL ADRH Note: Bit7 D1 D9 Bit6 D0 D8 Bit5 3/4 D7 Bit4 3/4 D6 Bit3 3/4 D5 Bit2 3/4 D4 Bit1 3/4 D3 Bit0 3/4 D2 Analog Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 0 1 ADCS0 ADCS1 2~6 7 3/4 TEST D0~D9 is A/D conversion result data bit LSB~MSB. ADRL (24H), ADRH (25H) Register Rev. 1.40 20 November 23, 2005 HT46R232/HT46C232 The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D converter : : ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START ; reset A/D clr START ; start A/D Polling_EOC: sz EOCB ; poll the ADCR register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,ADRH ; read conversion result high byte value from the ADRH register mov adrh_buffer,a ; save result to user defined memory mov a,ADRL ; read conversion result low byte value from the ADRL register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next A/D conversion Example: using interrupt method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov mov a,00100000B ADCR,a : ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START clr ADF set EADI set EMI : : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a mov a,STATUS mov status_stack,a : : mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a clr START set START clr START : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a mov a,acc_stack reti ; reset A/D ; start A/D ; clear ADC interrupt request flag ; enable ADC interrupt ; enable global interrupt ; save ACC to user defined memory ; save STATUS to user defined memory ; read conversion result high byte value from the ADRH register ; save result to user defined register ; read conversion result low byte value from the ADRL register ; save result to user defined register ; reset A/D ; start A/D ; restore STATUS from user defined memory ; restore ACC from user defined memory Rev. 1.40 21 November 23, 2005 HT46R232/HT46C232 M in im u m START o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d EOCB PC R2~ PCR0 A /D tA 000B DCS s a m p lin g tim e A /D tA DCS s a m p lin g tim e A /D tA DCS s a m p lin g tim e 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n 100B 100B 101B AC S2~ ACS0 000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : A /D c lo c k m u s t b e fS tA D C S = 3 2 tA D tA D C = 7 6 tA D YS 010B S ta rt o f A /D c o n v e r s io n 000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n 001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n d o n 't c a r e E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e tA D C c o n v e r s io n tim e YS A /D tA D C c o n v e r s io n tim e A /D /2 , fS /8 o r fS YS /3 2 A/D Conversion Timing Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: * The low voltage (0.9V~VLVR) has to remain in their The relationship between VDD and VLVR is shown below. VDD 5 .5 V V OPR 5 .5 V V 3 .0 V 2 .2 V LVR original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. * The LVR uses the OR function with the external RES 0 .9 V signal to perform chip reset. Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. V 5 .5 V DD V LVR LVR D e te c t V o lta g e 0 .9 V 0V R e s e t S ig n a l R eset *1 N o r m a l O p e r a tio n *2 R eset Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.40 22 November 23, 2005 HT46R232/HT46C232 I2C Bus Serial Interface I C Bus is implemented in the device. The I C Bus is a bidirectional two-wire lines. The data line and clock line are implement in SDA pin and SCL pin. The SDA and SCL are NMOS open drain output pin. They must connect a pull-high resistor respectively. Using the I2C Bus, the device has two ways to transfer data. One is in slave transmit mode, the other is in slave receive mode. There are four registers related to I2C Bus; HADR([20H]), HCR([21H]), HSR([22H]), HDR([23H]). The HADR register is the slave address setting of the device, if the master sends the calling address which match, it means that this device is selected. The HCR is I2C Bus control register which defines the device enable or disable the I2C Bus as a transmitter or as a receiver. The HSR is I2C Bus status register, it responds with the I2C Bus status. The HDR is input/output data register, data to transmit or receive must be via the HDR register. The I2C Bus control register contains three bits. The HEN bit defines whether to enable or disable the I2C Bus. If the data wants to transfer via I2C Bus, this bit must be set. The HTX bit defines whether the I2C Bus is in transmit or receive mode. If the device is as a transmitter, this bit must be set to 1. The TXAK defines the transmit acknowledge signal, when the device received 8-bit data, the device sends this bit to I2C Bus at the 9th clock. If the receiver wants to continue to receive the next data, this bit must be reset to 0 before receiving data. The I2C Bus status register contains 5 bits. The HCF bit is reset to 0 when one data byte is being transferred. If one data transfer is completed, this bit is set to 1. The HAAS bit is set 1 when the address is match, and the I2C Bus interrupt request flag is set to 1. If the interrupt is enabled and the stack is not full, a subroutine call to location 10H will occur. Writing data to the I2C Bus control register clears HAAS bit. If the address is not match, this bit is reset to 0. The HBB bit is set to respond the I2C Bus is busy. It mean that a START signal is detected. This bit is reset to 0 when the I2C Bus is not busy. It means that a STOP signal is detected and the I2C Bus is free. The SRW bit defines the read/write command bit, if the calling address is match. When HAAS is set to 1, the device check SRW bit to determine whether the de2 2 vice is working in transmit or receive mode. When SRW bit is set 1, it means that the master wants to read data from I2C Bus, the slave device must write data to I2C Bus, so the slave device is working in transmit mode. When SRW is reset to 0, it means that the master wants to write data to I2C Bus, the slave device must read data from the bus, so the slave device is working in receive mode. The RXAK bit is reset 0 indicates an acknowledges signal has been received. In the transmit mode, the transmitter checks RXAK bit to know the receiver which wants to receive the next data byte, so the transmitter continue to write data to the I2C Bus until the RXAK bit is set to 1 and the transmitter releases the SDA line, so that the master can send the STOP signal to release the bus. The HADR bit7-bit1 define the device slave address. At the beginning of transfer, the master must select a device by sending the address of the slave device. The bit 0 is unused and is not defined. If the I2C Bus receives a start signal, all slave device notice the continuity of the 8-bit data. The front of 7 bits is slave address and the first bit is MSB. If the address is match, the HAAS status bit is set and generate an I2C Bus interrupt. In the ISR, the slave device must check the HAAS bit to know the I2C Bus interrupt comes from the slave address that has match or completed one 8-bit data transfer. The last bit of the 8-bit data is read/write command bit, it responds in SRW bit. The slave will check the SRW bit to know if the master wants to transmit or receive data. The device check SRW bit to know it is as a transmitter or receiver. Bit7~Bit1 Slave Address 3/4 means undefined HADR (20H) Register The HDR register is the I2C Bus input/output data register. Before transmitting data, the HDR must write the data which needs to be transmitted. Before receiving data, the device must dummy read data from HDR. Transmit or Receive data from I2C Bus must be via the HDR register. At the beginning of the transfer of the I2C Bus, the device must initial the bus, the following are the notes for initialing the I2C Bus: Bit0 3/4 Rev. 1.40 23 November 23, 2005 HT46R232/HT46C232 S ta rt W r ite S la v e A d d re s s to H A D R SET HEN D is a b le CLR EH I P o ll H IF to d e c id e w h e n to g o to I2C B u s IS R I2C B u s In te rru p t= ? E n a b le SET EHI W a it fo r In te r r u p t G o to M a in P r o g r a m G o to M a in P r o g r a m S ta rt No HAAS=1 ? Yes Yes Yes No No HTX=1 ? SRW =1 ? R e a d fro m HDR SET HTX C LR H TX C LR TXAK RETI Yes RXAK=1 ? No C LR H TX C LR TXAK W r ite to H D R W r ite to H D R D um m y R ead F ro m H D R RETI RETI D um m y R ead fro m H D R RETI RETI Rev. 1.40 24 November 23, 2005 HT46R232/HT46C232 Note: 1: Write the I2C Bus address register (HADR) to define its own slave address. 2: Set HEN bit of I2C Bus control register (HCR) bit 0 to enable the I2C Bus. Bit No. 0~2 3 4 5~6 7 Label 3/4 TXAK HTX 3/4 HEN Unused bit, read as 0 Enable/disable transmit acknowledge (0= acknowledge; 1= dont acknowledge) Defines the transmit/receive mode (0= receive mode; 1= transmit) Unused bit, read as 0 Enable/disable I2C Bus function (0= disable; 1= enable) HCR (21H) Register 3: Set EHI bit of the interrupt control register 1 (INTC1) bit 0 to enable the I2C Bus interrupt. Bit No. 0 1 2 3~4 5 6 7 Label RXAK 3/4 SRW 3/4 HBB HAAS HCF Function RXAK is cleared to 0 when the master receives an 8-bit data and acknowledgment at the 9th clock, RXAK is set to 1 means not acknowledged. Unused bit, read as 0 SRW is set to 1 when the master wants to read data from the I2C Bus, so the slave must transmit data to the master. SRW is cleared to 0 when the master wants to write data to the I2C Bus, so the slave must receive data from the master. Unused bit, read as 0 HBB is set to 1 when I2C Bus is busy and HBB is cleared to 0 means that the I2C Bus is not busy. HAAS is set to 1 when the calling address has matched, and I2C Bus interrupt will occur and HCF is set. HCF is cleared to 0 when one data byte is being transferred, HCF is set to 1 indicating 8-bit data communication has been finished. HSR (22H) Register SCL S ta rt S la v e A d d r e s s SRW ACK Function SDA 1 0 1 1 0 1 0 1 0 SCL D a ta ACK S to p 1 SDA S=S SA= SR= M =S D=D A=A P=S S ta rt (1 S la v e SRW la v e d a ta (8 C K (R to p (1 SA 0 0 1 0 1 0 0 b it) A d d r e s s ( 7 b its ) b it ( 1 b it) e v ic e s e n d a c k n o w le d g e b it ( 1 b it) b its ) X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it) b it) SR M D A D A S SA SR M D A D A P I2C Communication Timing Diagram Rev. 1.40 25 November 23, 2005 HT46R232/HT46C232 Start Signal The START signal is generated only by the master device. The other device in the bus must detect the START signal to set the I2C Bus busy bit (HBB). The START signal is SDA line from high to low, when SCL is high. SCL SDA Acknowledge Bit One of the slave device generates an acknowledge signal, when the slave address is matched. The master device can check this acknowledge bit to know if the slave device accepts the calling address. If no acknowledge bit, the master must send a STOP bit and end the communication. When the I2C Bus status register bit 6 HAAS is high, it means the address is matched, so the slave must check SRW as a transmitter (set HTX) to 1 or as a receiver (clear HTX) to 0. SCL SDA Start Bit Slave Address The master must select a device for transferring the data by sending the slave device address after the START signal. All device in the I2C Bus will receive the I2C Bus slave address (7 bits) to compare with its own slave address (7 bits). If the slave address is matched, the slave device will generate an interrupt and save the following bit (8th bit) to SRW bit and sends an acknowledge bit (low level) to the 9th bit. The slave device also sets the status flag (HAAS), when the slave address is matched. In interrupt subroutine, check HAAS bit to know whether the I2C Bus interrupt comes from a slave address that is matched or a data byte transfer is completed. When the slave address is matched, the device must be in transmit mode or receive mode and write data to HDR or dummy read from HDR to release the SCL line. SRW Bit The SRW bit means that the master device wants to read from or write to the I2C Bus. The slave device check this bit to understand itself if it is a transmitter or a receiver. The SRW bit is set to 1 means that the master wants to read data from the I2C Bus, so the slave device must write data to a bus as a transmitter. The SRW is cleared to 0 means that the master wants to write data to the I2C Bus, so the slave device must read data from the I2C Bus as a receiver. Stop Bit Data Byte The data is 8 bits and is sent after the slave device has acknowledged the slave address. The first bit is MSB and the 8th bit is LSB. The receiver sends the acknowledge signal (0) and continues to receive the next one byte data. If the transmitter checks and theres no acknowledge signal, then it release the SDA line, and the master sends a STOP signal to release the I2C Bus. The data is stored in the HDR register. The transmitter must write data to the HDR before transmitting data and the receiver must read data from the HDR after receiving data. SCL SDA S to p b it D a ta s ta b le D a ta a llo w change S ta r t b it Data Timing Diagram Receive Acknowledge Bit When the receiver wants to continue to receive the next data byte, it generates an acknowledge bit (TXAK) at the 9th clock. The transmitter checks the acknowledge bit (RXAK) to continue to write data to the I2C Bus or change to receive mode and dummy read the HDR register to release the SDA line and the master sends the STOP signal. Rev. 1.40 26 November 23, 2005 HT46R232/HT46C232 Options The following shows kinds of options in the device. ALL the options must be defined to ensure proper system function. Options OSC type selection. This option is to decide if an RC or crystal oscillator is chosen as system clock. WDT source selection. There are three types of selection: on-chip RC oscillator, instruction clock or disable the WDT. CLRWDT times selection. This option defines how to clear the WDT by instruction. One time means that the CLR WDT instruction can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then WDT can be cleared. Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT by a falling edge. (Bit option) Pull-high selection. This option is to decide whether a pull-high resistance is visible or not in the input mode of the I/O ports. PA and PB are bit option; PC, PD and PF are port option. PFD selection. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively. PWM selection: (7+1) or (6+2) mode PD0: level output or PWM0 output PD1: level output or PWM1 output PD2: level output or PWM2 output PD3: level output or PWM3 output WDT time-out period selection. 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS. I2C Bus function: enable or disable LVR selection. LVR has enable or disable options Rev. 1.40 27 November 23, 2005 HT46R232/HT46C232 Application Circuits V DD 0 .0 1 m F * 100kW 0 .1 m F 10kW VDD RES PA0~PA P A 3 /P F PA P A 5 /IN P A 6 /S D P A 7 /S C D ~ 2 4 T A L V DD 0 .1 m F * VSS P B 0 /A N 0 P B 7 /A N 7 PC 0~PC 7 R 470pF OSC OSC1 fS YS R C S y s te m O s c illa to r 30kW OSC2 OSC1 C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r OSC C ir c u it S e e R ig h t S id e OSC1 OSC2 P D 0 /P W M 0 P D 3 /P W M 3 PD 4~PD 7 PF0~PF7 TM R0 TM R1 C1 ~ C2 R1 OSC2 OSC C ir c u it H T 4 6 R 2 3 2 /H T 4 6 C 2 3 2 The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator C1, C2 0pF 10pF 0pF 25pF 25pF 35pF 300pF 300pF 300pF R1 10kW 12kW 10kW 10kW 10kW 27kW 9.1kW 10kW 10kW The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.40 28 November 23, 2005 HT46R232/HT46C232 Instruction Set Summary Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z Rev. 1.40 29 November 23, 2005 HT46R232/HT46C232 Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected (1) : If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (2) (3) (1) (4) Rev. 1.40 30 November 23, 2005 HT46R232/HT46C232 Instruction Definition ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m] Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m] Rev. 1.40 31 November 23, 2005 HT46R232/HT46C232 AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m] Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m] Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.40 32 November 23, 2005 HT46R232/HT46C232 CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0 Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) CLR WDT1 Description Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CLR WDT2 Description Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) CPL [m] Description Operation Affected flag(s) Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.40 33 November 23, 2005 HT46R232/HT46C232 CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Operation Affected flag(s) Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 DECA [m] Description Operation Affected flag(s) Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Rev. 1.40 34 November 23, 2005 HT46R232/HT46C232 HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1 Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m] Rev. 1.40 35 November 23, 2005 HT46R232/HT46C232 MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m] Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] Rev. 1.40 36 November 23, 2005 HT46R232/HT46C232 RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RETI Description Operation Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RL [m] Description Operation Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RLA [m] Description Operation Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.40 37 November 23, 2005 HT46R232/HT46C232 RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) RR [m] Description Operation Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRA [m] Description Operation Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) RRC [m] Description Operation Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Affected flag(s) Rev. 1.40 38 November 23, 2005 HT46R232/HT46C232 RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O Operation Affected flag(s) Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SDZA [m] Description Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) Rev. 1.40 39 November 23, 2005 HT46R232/HT46C232 SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1 Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SIZA [m] Description Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Operation Affected flag(s) SNZ [m].i Description Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0 Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rev. 1.40 40 November 23, 2005 HT46R232/HT46C232 SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1 Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1 Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1 Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4 Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.40 41 November 23, 2005 HT46R232/HT46C232 SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0 Operation Affected flag(s) TO 3/4 SZ [m].i Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0 Operation Affected flag(s) TO 3/4 TABRDC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) TABRDL [m] Description Operation Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Affected flag(s) Rev. 1.40 42 November 23, 2005 HT46R232/HT46C232 XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m] Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x Rev. 1.40 43 November 23, 2005 HT46R232/HT46C232 Package Information 28-pin SKDIP (300mil) Outline Dimensions A 28 B 1 15 14 H C D E F G a I Symbol A B C D E F G H I a Dimensions in mil Min. 1375 278 125 125 16 50 3/4 295 330 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 1395 298 135 145 20 70 3/4 315 375 15 Rev. 1.40 44 November 23, 2005 HT46R232/HT46C232 28-pin SOP (300mil) Outline Dimensions 28 A 15 B 1 14 C C' G H D E F a Symbol A B C C D E F G H a Dimensions in mil Min. 394 290 14 697 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 3/4 38 12 10 Rev. 1.40 45 November 23, 2005 HT46R232/HT46C232 48-pin SSOP (300mil) Outline Dimensions 48 A 25 B 1 C C' 24 G H a F D E Symbol A B C C D E F G H a Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8 Rev. 1.40 46 November 23, 2005 HT46R232/HT46C232 Product Tape and Reel Specifications Reel Dimensions T2 D A B C T1 SOP 28W (300mil) Symbol A B C D T1 T2 SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 1000.1 13.0+0.5 -0.2 2.00.5 32.2+0.3 -0.2 38.20.2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2 Rev. 1.40 47 November 23, 2005 HT46R232/HT46C232 Carrier Tape Dimensions D E F P0 P1 t W C B0 D1 P K0 A0 SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.1 11.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 10.850.1 18.340.1 2.970.1 0.350.01 21.3 Rev. 1.40 48 November 23, 2005 HT46R232/HT46C232 D E F W C B0 P0 P1 t D1 P K2 A0 K1 SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.00.3 16.00.1 1.750.1 14.20.1 2.0 Min. 1.5+0.25 4.00.1 2.00.1 12.00.1 16.200.1 2.40.1 3.20.1 0.350.05 25.5 Rev. 1.40 49 November 23, 2005 HT46R232/HT46C232 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2005 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.40 50 November 23, 2005 |
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